The present invention relates to a pipeline A/D converter.
As digitization proceeds in the audiovisual field and the information and communication field, A/D converters being used as key devices in the fields are requested to have higher speed, higher resolution and lower power consumption.
A pipeline A/D converter in accordance with a conventional example will be described below with reference to FIG. 12.
FIG. 12 shows the configuration of the pipeline A/D converter in accordance with the conventional example. The operational amplifier 2 is equipped with means for sampling and holding analog input signals input from analog input signal terminals 6 and 7. Digital output signals output from the M pipe stages 1201a to 1201e are input to the digital demodulator circuit 8 and subjected to arithmetic processing, and an N-bit digital signal is output.
The M stages 1201a to 1201e have the same configuration. The number of the stages varies with each A/D converter. In the conventional example, the number of the stages is set at M. The configuration of the stage 1201a will be described below. The stage 1201a comprises an operational amplifier 1203, an A/D converter 4 and a D/A converter 5.
The output signals of the preceding stage (the operational amplifier 2) are input to the A/D converter 4 and subjected to comparison processing, and digital output signals are output. The digital output signal output from the A/D converter 4 and input to the D/A converter 5 is subjected to digital processing, and voltage values corresponding to the input digital signal are output. The output signals of the preceding stage (the operational amplifier 2) and the output signals of the D/A converter 5 are input to the operational amplifier 1203, subjected to addition (actually subtraction), amplified and output. The operational amplifier 1203 constituting each stage of this pipeline A/D converter is generally equipped with capacitance devices (capacitors). These capacitance devices (capacitors) serve as very important elements in determining the allowable conversion processing rate, power consumption and resolution of the A/D converter.
FIG. 13 is a view showing a configuration of the operational amplifier 1203 of the pipeline A/D converter in accordance with the conventional example. The peripheral circuit 21a comprises capacitance devices (capacitors) 12a and 12b, and switches 13a, 13b, 13c, 13d, 13e and 13f that are turned ON/OFF according to the clock timing shown in FIG. 4. The peripheral circuit 21b has the same configuration as that of the peripheral circuit 21a. 
Next, the working of the operational amplifier 1203 shown in FIG. 13 will be described below. The operation of the peripheral circuit 21a is the same as that of the peripheral circuit 21b. The operation of the peripheral circuit 21a is described in the following description. In FIG. 13, control signal CLK1 (FIG. 4) is input to the switches 13a, 13b, 13e and 13f. These switches are turned ON in a period A and turned OFF in the other periods. Control signal CLK2 (FIG. 4) is input to the switches 13c, 13d. These switches are turned ON in a period B and turned OFF in the other periods.
First, in the period A shown in FIG. 4, the switches 13a, 13b, 13e and 13f shown in FIG. 13 are turned ON, and the other switches are turned OFF. The capacitance device (capacitor) 12a having a capacitance value C1 is charged with the charge corresponding to the voltage difference between the voltage of the signal from the analog signal input terminal 14a and the DC bias voltage from the DC bias input terminal 15a. At this time, the analog signal output terminal 19a is short-circuited to the DC bias input terminal 17a, and the voltage at the analog signal output terminal 19abecomes the DC bias voltage which is input from the DC bias input terminal 17a. 
Next, in the period B shown in FIG. 4, the switches 13c and 13d shown in FIG. 13 are turned ON, and the other switches are turned OFF. The charge of the capacitance device (capacitor) 12a having been charged in the period A shown in FIG. 4 is distributed to the capacitance device (capacitor) 12b having a capacitance value C2. According to the law of conservation of charge, the differential amplifier circuit 11 amplifies the input signals from the analog signal input terminals 14a and 14b by the ratio of the capacitances of the capacitance devices (capacitors) 12a and 12b, that is, C1/C2. The differential amplifier circuit 11 outputs the amplified analog signals from the analog signal output terminals 19a and 19b. 
FIG. 14 is a view showing another configuration of the operational amplifier 1203 of the pipeline A/D converter in accordance with the conventional example. The peripheral circuit 21a comprises capacitance devices (capacitors) 12a and 12b, and switches 13a, 13b, 13c, 13d, 13e and 13fthat are turned ON/OFF according to the clock timing shown in FIG. 4. The peripheral circuit 21b has the same configuration as that of the peripheral circuit 21a. 
Next, the working of the operational amplifier 1203 shown in FIG. 14 will be described below. The operation of the peripheral circuit 21a is the same as that of the peripheral circuit 21b. The operation of the peripheral circuit 21a is described in the following description. In FIG. 14, control signal CLK1 (FIG. 4) is input to the switches 13a, 13b, 13e and 13f. These switches are turned ON in the period A and turned OFF in the other periods. Control signal CLK2 (FIG. 4) is input to the switches 13c, 13d. These switches are turned ON in the period B and turned OFF in the other periods.
In the period A shown in FIG. 4, the switches 13a, 13b, 13e and 13f are turned ON, and the other switches are turned OFF. The capacitance device (capacitor) 12a having a capacitance value C1 and the capacitance device (capacitor) 12b having a capacitance value C2 are charged with the charge corresponding to the voltage difference between the voltage of the signal from the analog signal input terminal 14a and the DC bias voltage from the DC bias input terminal 15a. At this time, the analog signal output terminal 19a is short-circuited to the DC bias input terminal 17a, and the voltage at the analog signal output terminal 19a becomes the DC bias voltage which is input from the DC bias input terminal 17a. 
In the period B shown in FIG. 4, the switches 13c and 13d shown in FIG. 14 are turned ON, and the other switches are turned OFF. The charges of the capacitance devices (capacitors) 12a and 12b, charged in the period A shown in FIG. 4, are redistributed. According to the law of conservation of charge, the differential amplifier circuit 11 amplifies the input signals from the analog signal input terminals 14a and 14b by the ratio of the capacitances of the capacitance devices (capacitors) 12a and 12b, that is, (C1+C2)/C2. The differential amplifier circuit 11 outputs the amplified analog signals from the analog signal output terminals 19a and 19b. 
In the multiple stages connected in series, the allowable operation range of the operational amplifier 1203 is approximately determined by gm/C wherein gm is the transconductance of the differential amplifier circuit 11 in the preceding stage and C is the capacitance value of the operational amplifier in the subsequent stage (driven by the differential amplifier circuit 11 in the preceding stage) (FIGS. 13 and 14). This exerts an influence on the signal settling performance in the allowable operation range of the operational amplifier 1203, thereby eventually exerting an influence on the allowable conversion processing rate of the A/D converter. The power consumption of the operational amplifier 1203 is also considered as described below. The current required to charge/discharge the charge corresponding to an output signal amplitude dV of the differential amplifier circuit 11 in a constant time dt using the differential amplifier 11 to the capacitance value C of the operational amplifier 1203 in the subsequent stage being connected in series is determined by C×dV/dt. The total of these currents of the operational amplifiers 1203 in all the stages determines almost all the power consumption of the A/D converter.
Patent document 1, Japanese Laid-open Patent Application No. 2003-198368, describes a conventional technology for reducing the power consumption of the whole of an A/D converter. According to the conventional technology described in Patent document 1, the current flowing in a differential amplifier circuit constituting an operational amplifier is controlled, whereby the transconductance gm of the differential amplifier circuit is changed and the resolution required for the A/D converter is changed. Hence, in the case that the performance of the A/D converter is higher than the performance required for the A/D converter, the current flowing in the differential amplifier circuit can be decreased, and the power consumption of the whole of the A/D converter can be reduced.
As described in “IEEE J. SOLID-STATE CIRCUITS, Vol. 36, pp. 1931-1936, December 2001 [A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR],” for the purpose of satisfying a resolution required for a pipeline A/D converter, the relative accuracy of the capacitances of the capacitance devices (FIGS. 13 and 14) constituting an operational amplifier determines the resolution of the A/D converter. Generally speaking, the larger the capacitance value, the higher the relative accuracy of the capacitance. It is thus known to be necessary to determine the capacitance value matching to the resolution on the basis of the relative accuracy of the capacitance.
As described above, the capacitance devices (capacitors) constituting the operational amplifier are very important to determine the allowable conversion processing rate, power consumption and resolution of the pipeline A/D converter. Conventionally, the capacitance values of the capacitance devices (capacitors) were fixed values matching to the performance required for the A/D converter.
As described above, in the conventional pipeline A/D converter, even in the case that the performance required for the A/D converter being used in a system is changed, the capacitance values of the capacitance devices (capacitors) of the operational amplifier constituting the pipeline A/D converter are fixed. As a result, the performance of the A/D converter cannot be changed. In the case that the performance of the A/D converter being used in the system is higher than the performance required for the A/D converter, the A/D converter has wasteful allowable conversion processing rate and wasteful resolution and consumes wasteful power, each wasted by the amount corresponding to the excess performance.
Furthermore, even in the case that the allowable conversion processing rate, resolution and power consumption of the A/D converter are lowered by controlling the current flowing in the differential amplifier circuit constituting the operational amplifier, as long as the capacitance values of the capacitance devices of the operational amplifier are fixed the reduction of the power consumption is determined by the fixed capacitance values. Therefore, further reduction of the power consumption cannot be attained.